Research
Our Approach
Our research program aims to solve the full range of problems to design the next generation of advanced computing systems, from edge devices and mobile platforms to high-performance computing (HPC) in servers and data centers for AI workloads.
- We identify unique design challenges and trade-offs in emerging compute platforms.
- This understanding allows us to create surrogate mathematical/ML models that capture the complexity of micro-architectures, the dataflow between cores (data communication patterns), etc.
- Next, we use these validated models to design novel ML-based methodologies to solve multi-objective design space exploration/optimization and runtime resource management, targeting energy efficiency, performance, and reliability.
Our research focuses on cross-layer hardware and software co-design spanning across applications, advanced packaging, and architecture – synergistically combining the strengths of ML and emerging compute technologies.
Emerging Compute Substrates
This thrust investigates design automation (EDA) challenges due to emerging non-ideal compute technologies. Compute- and memory-intensive transformer models necessitate heterogeneous chiplet integration. Compute-in-memory (CIM) and Silicon-Photonics(SiPh) are few promising ways to efficiently accelerate such models. Since emerging technologies suffer from non-idealities due to immature fabrication, novel design automation methodologies are required to enable heterogeneous integration with the ‘mature’ CMOS-based designs. This research theme goes beyond classical computing to solve Quantum EDA challenges as well.
Neuromorphic Computing
Computing at the edge presents new challenges due to limited battery and memory storage, requiring ultra-low-power design and parameter-efficient neural networks. Neuromorphic computing has the potential to reduce the energy consumption by 100×, specifically for event-driven tasks such as gesture and motion recognition. We focus on the following:
- Accelerating spiking LLMs on multi-chiplet and wafer-scale chips
- Training algorithms beyond back-propagation
- Multi-modal learning (e.g., audio+visual)
Representative Publications: Coming soon
Reliability in Advanced Packaging
In addition to power and performance objectives, we consider package reliability aspects, such as IR drop, warpage, mechanical stress, and electromigration (EM). These reliability issues can cause chip failure in mission-critical scenarios. For instance, package warpage causes stress in micro-bumps between the chiplet and interposer, causing cracks and voids over time. This requires careful design and co-optimization of the architecture and package. We are focusing on 2.5D and 3D stacks.
Representative Publications: Coming soon
Collaborations
We welcome collaborators in datacenter, agriculture, and space applications, and beyond.